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DESCRIPTION

The Aeroflex ACT5271 is a highly integrated superscalar microprocessor that implements a superset of the MIPS IV Instruction Set Architecture(ISA). It has a high performance 64-bit integer unit, a high throughput, fully pipelined 64-bit floating point unit, an operating system friendly memory management unit with a 48-entry fully associative TLB, a 32 KByte 2-way set associative instruction cache, a 32 KByte 2-way set associative data cache, and a high-performance 64-bit system interface with support for an optional external secondary cache. The ACT5271 can issue both an integer and a floating point instruction in the same cycle.

Features

■ Full militarized QED RM5271 microprocessor

■ Dual Issue superscalar microprocessor - can issue one integer and one floating-point instruction per cycle

● 150, 200, 250 MHz operating frequencies – Consult Factory for latest speeds

● 345 Dhrystone2.1 MIPS maximum

● SPECInt95 7.3, SPECfp95 8.3 maximum

■ High performance system interface compatible with RM7000, RM5270, RM5260, RM5261, R4600, R4700 and R5000

● Up to 125MHz memory bus operation for a 1000MBps bandwidth from CPU to L2 cache and main memory

● 64-bitmultiplexed system address/data bus for optimum price/ performance with high performance write protocols to maximize uncached write bandwidth

● Supports 1/2 clock divisors (2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9)

● IEEE 1149.1 JTAG boundary scan

■ Integrated on-chip caches

● 32KB/32KB instruction/data -both 2 way set associative

● Virtually indexed, physically tagged

● Write-back and write-through on per page basis

● Pipeline restart on first double for data cache misses

■ Integrated secondary cache controller (R5000 compatible)

● Supports 512K or 2MByte block write-through secondary

■ Integrated memory management unit

● Fully associative joint TLB (shared by I and D translations)

● 48 dual entries map 96 pages

● Variable page size (4KB to 16MB in 4x increments)

■ High-performance floating point unit - up to 532 MFLOPS

● Single cycle repeat rate for common single precision operations and some double precision operations

● Two cycle repeat rate for double precision multiply and double precision combined multiply-add operations

● Single cycle repeat rate for single precision combined multiplyadd operation

■ MIPS IV instruction set

● Floating point multiply-add instruction increases performance in signal processing and graphics applications

● Conditional moves to reduce branch frequency

● Index address modes (register + register)

■ Embedded application enhancements

● Specialized DSP integer Multiply-Accumulate instruction and 3 operand multiply instruction

● I and D cache locking by set

● Optional dedicated exception vector for interrupts

■ Fully static CMOS design with power down logic

● Standby reduced power mode with WAIT instruction

● 4.2 Watts typical power @ 200MHz

● 2.5V core with 3.3V IO’s

■ 208-lead CQFP, cavity-up package (F17)

■ 208-lead CQFP, inverted footprint (F24), Intended to duplicate the commercial QED footprint

■ 179-pin PGA package (Future Product) (P10)