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General Description

The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process.

The A67P83181, A67P73361 SRAMs integrate a 256K X 18, 128K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during Write-Read alternation.

Features

¡ö Fast access time: 6.5/7.5/8.5 ns (153, 133, 117 MHz)

¡ö Zero Bus Latency between READ and WRITE cycles allows 100 bus utilization

¡ö Signal +2.5V ¡À 5 power supply

¡ö Individual Byte Write control capability

¡ö Clock enable ( CEN) pin to enable clock and suspend operations

¡ö Clock-controlled and registered address, data and control signals

¡ö Registered output for pipelined applications

¡ö Three separate chip enables allow wide range of options for CE control, address pipelining

¡ö Internally self-timed write cycle

¡ö Selectable BURST mode (Linear or Interleaved)

¡ö SLEEP mode (ZZ pin) provided

¡ö Available in 100 pin LQFP package