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DESCRIPTION

M2S56D20ATP / AKT is a 4-bank x 16777216-word x 4-bit,

M2S56D30ATP / AKT is a 4-bank x 8388608-word x 8-bit,

M2S56D40ATP/ AKT is a 4-bank x 4194304-word x 16-bit,

double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK.Input data is registered on both edges of data strobes, and output data and data strobe are referenced on both edges of CLK. The M2S56D20/30/40A achieve very high speed data rate up to 166MHz(-60), 133MHz(-75A/-75) and are suitable for main memory in computer systems.

FEATURES

- VDD=VDDQ=2.5V+0.2V

- Double data rate architecture; two data transfers per clock cycle

- Bidirectional, data strobe (DQS) is transmitted/received with data

- Differential clock inputs (CLK and /CLK)

- DLL aligns DQ and DQS transitions

- Commands are entered on each positive CLK edge

- Data and data mask are referenced to both edges of DQS

- 4-bank operations are controlled by BA0, BA1 (Bank Address)

- /CAS latency- 2.0/2.5 (programmable)

- Burst length- 2/4/8 (programmable)

- Burst type- sequential / interleave (programmable)

- Auto precharge / All bank precharge is controlled by A10

- 8192 refresh cycles /64ms (4 banks concurrent refresh)

- Auto refresh and Self refresh

- Row address A0-12 / Column address A0-9,11(x4) / A0-9(x8) / A0-8(x16)

- SSTL_2 Interface

- Both 66-pin TSOP Package and 64-pin Small TSOP Package

M2S56D*0ATP: 0.65mm lead pitch 66-pin TSOP Package

M2S56D*0AKT: 0.4mm lead pitch 64-pin Small TSOP Package

- JEDEC standard

- Low Power for the Self Refresh Current

Ultra Low Power Version : ICC6 < 1mA ( -60UL , -75AU , -75UL )

Low Power Version : ICC6