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The MPC8541E integrates a PowerPC? processor core built on Power Architecture? technology with system logic required for networking, telecommunications, and wireless infrastructure applications. The MPC8541E is a member of the PowerQUICC? III family of devices that combine system-level support for industry-standard interfaces with processors that implement the embedded category of the Power Architecture technology. For functional characteristics of the processor, refer to the MPC8555E PowerQUICC? III Integrated Communications Processor Reference Manual.

Overview

The following section provides a high-level overview of the MPC8541E features. Figure 1 shows the major functional units within the MPC8541E.

Key Features

The following lists an overview of the MPC8541E feature set.

? Embedded e500 Book E-compatible core

¡ª High-performance, 32-bit Book E-enhanced core that implements the PowerPC architecture

¡ª Dual-issue superscalar, 7-stage pipeline design

¡ª 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection

¡ª Lockable L1 caches¡ªentire cache or on a per-line basis

¡ª Separate locking for instructions and data

¡ª Single-precision floating-point operations

¡ª Memory management unit especially designed for embedded applications

¡ª Enhanced hardware and software debug support

¡ª Dynamic power management

¡ª Performance monitor facility

? Security Engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP, IEEE Std 802.11i?, iSCSI, and IKE processing. The Security Engine contains 4 Crypto-channels, a Controller, and a set of crypto Execution Units (EUs). The Execution Units are:

¡ª Public Key Execution Unit (PKEU) supporting the following:

¨C RSA and Diffie-Hellman

¨C Programmable field size up to 2048-bits

¨C Elliptic curve cryptography

¨C F2m and F(p) modes

¨C Programmable field size up to 511-bits

¡ª Data Encryption Standard Execution Unit (DEU)

¨C DES, 3DES

¨C Two key (K1, K2) or Three Key (K1, K2, K3)

¨C ECB and CBC modes for both DES and 3DES

¡ª Advanced Encryption Standard Unit (AESU)

¨C Implements the Rinjdael symmetric key cipher

¨C Key lengths of 128, 192, and 256 bits.Two key

¨C ECB, CBC, CCM, and Counter modes

¡ª ARC Four execution unit (AFEU)

¨C Implements a stream cipher compatible with the RC4 algorithm

¨C 40- to 128-bit programmable key

¡ª Message Digest Execution Unit (MDEU)

¨C SHA with 160-bit or 256-bit message digest

¨C MD5 with 128-bit message digest

¨C HMAC with either algorithm

¡ª Random Number Generator (RNG)

¡ª 4 Crypto-channels, each supporting multi-command descriptor chains

¨C Static and/or dynamic assignment of crypto-execution units via an integrated controller

¨C Buffer size of 256 Bytes for each execution unit, with flow control for large data sizes

? High-performance RISC CPM

¡ª Two full-duplex fast communications controllers (FCCs) that support the following protocol:

¨C IEEE Std 802.3?/Fast Ethernet (10/100)

¡ª Serial peripheral interface (SPI) support for master or slave

¡ª I2C bus controller

¡ª General-purpose parallel ports¡ª16 parallel I/O lines with interrupt capability

? 256 Kbytes of on-chip memory

¡ª Can act as a 256-Kbyte level-2 cache

¡ª Can act as a 256-Kbyte or two 128-Kbyte memory-mapped SRAM arrays

¡ª Can be partitioned into 128-Kbyte L2 cache plus 128-Kbyte SRAM

¡ª Full ECC support on 64-bit boundary in both cache and SRAM modes

¡ª SRAM operation supports relocation and is byte-accessible

¡ª Cache mode supports instruction caching, data caching, or both

¡ª External masters can force data to be allocated into the cache through programmed memory ranges or special transaction types (stashing).

¡ª Eight-way set-associative cache organization (1024 sets of 32-byte cache lines)

¡ª Supports locking the entire cache or selected lines

¨C Individual line locks set and cleared through Book E instructions or by externally mastered transactions

¡ª Global locking and flash clearing done through writes to L2 configuration registers

¡ª Instruction and data locks can be flash cleared separately

¡ª Read and write buffering for internal bus accesses (Continue....)