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Introduction

The 68HC(9)12D60 microcontroller unit (MCU) is a 16-bit device available in two package options, 80-pin QFP and 112-pin TQFP. On chip peripherals include a 16-bit central processing unit (CPU12), 60K bytes of flash EEPROM (68HC912D60) or ROM (68HC12D60), 2K bytes of RAM, 1K bytes of EEPROM, two asynchronous serial communication interfaces (SCI), a serial peripheral interface (SPI), an enhanced capture timer (ECT), two (one on 80QFP) 8-channel,10-bit analog-to-digital converters (ATD), a four-channel pulse-width modulator (PWM), and a CAN 2.0 A, B software compatible module (MSCAN12). System resource mapping, clock generation, interrupt control and bus interfacing are managed by the lite integration module (LIM). The 68HC(9)12D60 has full 16-bit data paths throughout, however, the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower cost systems. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. In addition to the I/O ports available in each module, 16 (2 on 80QFP) I/O port pins are available with Key-Wake-Up capability from STOP or WAIT mode.

Features

? 16-bit CPU12

¨C Upward compatible with M68HC11 instruction set

¨C Interrupt stacking and programmer¡¯s model identical to M68HC11

¨C 20-bit ALU

¨C Instruction queue

¨C Enhanced indexed addressing

? Multiplexed bus

¨C Single chip or expanded

¨C 16 address/16 data wide or 16 address/8 data narrow mode

? Two 8-bit ports with key wake-up interrupt (2 pins only are available on 80QFP) and one I2C start bit detector (112TQFP only)

? Memory

¨C 60K byte flash EEPROM, made of a 28K module and a 32K module with 8K bytes protected BOOT section in each module (68HC912D60)

¨C 60K byte ROM (68HC12D60)

¨C 1K byte EEPROM

¨C 2K byte RAM

? Analog-to-digital converters

¨C 2 x 8-channels, 10-bit resolution in 112TQFP

¨C 1 x 8-channels, 8-bit resolution in 80QFP

? 1M bit per second, CAN 2.0 A, B software compatible module

¨C Two receive and three transmit buffers

¨C Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit

¨C Four separate interrupt channels for Rx, Tx, error and wake-up

¨C Low-pass filter wake-up function

¨C In 80QFP, only TxCAN and RxCAN pins are available

¨C Loop-back for self test operation

¨C Programmable link to a timer input capture channel, for time stamping and network synchronization.

? Enhanced capture timer (ECT)

¨C 16-bit main counter with 7-bit prescaler

¨C 8 programmable input capture or output compare channels; 4 of the 8 input captures with buffer

¨C Input capture filters and buffers, three successive captures on four channels, or two captures on four channels with a capture/compare selectable on the remaining four

¨C Four 8-bit or two 16-bit pulse accumulators

¨C 16-bit modulus down-counter with 4-bit prescaler

¨C Four user-selectable delay counters for signal filtering

? 4 PWM channels with programmable period and duty cycle

¨C 8-bit 4-channel or 16-bit 2-channel

¨C Separate control for each pulse width and duty cycle

¨C Center- or left-aligned outputs

¨C Programmable clock select logic with a wide range of frequencies

? Serial interfaces

¨C Two asynchronous serial communications interfaces (SCI)

¨C MI-Bus implemented on final devices

¨C Synchronous serial peripheral interface (SPI)

? LIM (light integration module)

¨C WCR (windowed COP watchdog, real time interrupt, clock monitor)

¨C ROC (reset and clocks)

¨C MEBI (multiplexed external bus interface)

¨C MBI (internal bus interface and map)

¨C INT (interrupt control)

? Clock generation

¨C Phase-locked loop clock frequency multiplier

¨C Limp home mode in absence of external clock

¨C Slow mode divider

¨C Low power 0.5 to 16 MHz crystal oscillator reference clock

? 112-Pin TQFP package or 80-pin QFP package

¨C Up to 68 general-purpose I/O lines, plus up to 18 input-only lines in 112TQFP or Up to 48 general-purpose I/O lines, plus up to 10 input-only lines in 80QFP

? 8MHz operation at 5V

? Development support

¨C Single-wire background debug? mode (BDM)

¨C On-chip hardware breakpoints