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Functional Description

Applications

The GS880F18/32/36BT-xxxV is a 9,437,184-bit (8,388,608- bit for x32 version) high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.

Features

? Flow Through operation; Pin 14 = No Connect

? 1.8 V or 2.5 V +10/–10 core power supply

? 1.8 V or 2.5 V I/O supply

? LBO pin for Linear or Interleaved Burst mode

? Internal input resistors on mode pins allow floating mode pins

? Byte Write (BW) and/or Global Write (GW) operation

? Internal self-timed write cycle

? Automatic power-down for portable applications

? JEDEC-standard 100-lead TQFP package

? RoHS-compliant 100-lead TQFP package available