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General description

PSoC? 6 MCU is a high-performance, ultra-low-power and secured MCU platform, purpose-built for IoT

applications. The PSoC? 63 with Bluetooth? LE product line, based on the PSoC? 6 MCU platform, is a

combination of a high-performance microcontroller with low-power flash technology, digital programmable

logic, high-performance analog-to-digital conversion and standard communication and timing peripherals.

The PSoC? 63 product line provides wireless connectivity with Bluetooth? LE 5.0 compliance.

Features

? 32-bit Dual CPU subsystem

- 150-MHz Arm? Cortex?-M4F (CM4) CPU with single-cycle multiply, floating point, and memory protection unit

(MPU)

- 100-MHz Cortex?-M0+ (CM0+) CPU with single-cycle multiply and MPU

- User-selectable core logic operation at either 1.1 V or 0.9 V

- Active CPU current slope with 1.1-V core operation

? Cortex?-M4: 40 μA/MHz

? Cortex?-M0+: 20 μA/MHz

- Active CPU current slope with 0.9-V core operation

? Cortex?-M4: 22 μA/MHz

? Cortex?-M0+: 15 μA/MHz

- Two DMA controllers with 16 channels each

? Memory subsystem

? 1-MB application flash, 32-KB auxiliary flash (AUXflash), and 32-KB supervisory flash (SFlash); read-while-write

(RWW) support. Two 8-KB flash caches, one for each CPU.

? 288-KB SRAM with power and data retention control

? One-time-programmable (OTP) 1-Kb eFuse array

? Bluetooth? Low Energy subsystem

- 2.4-GHz RF transceiver with 50-? antenna drive

- Digital PHY

- Link Layer engine supporting master and slave modes

- Programmable TX power: up to 4 dBm

- RX sensitivity: –95 dBm

- RSSI: 4-dB resolution

- 5.7-mA Tx (0 dBm) and 6.7 mA RX (2 Mbps) current with 3.3-V supply and internal SIMO Buck converter

- Link Layer engine supports four connections simultaneously

- Supports 2 Mbps data rate

? Low-power 1.7-V to 3.6-V operation

- Six power modes for fine-grained power management

- Deep Sleep mode current of 7 μA with 64-KB SRAM retention

- On-chip Single-In Multiple Out (SIMO) DC-DC buck converter, <1 μA quiescent current

- Backup domain with 64 bytes of memory and real-time clock

? Flexible clocking options

- 8-MHz Internal Main Oscillator (IMO) with ±2 accuracy

- Ultra-low-power 32-kHz Internal Low-speed Oscillator (ILO)

- On-chip crystal oscillators (16 to 35 MHz, and 32 kHz)

- Phase-locked loop (PLL) for multiplying clock frequencies

- Frequency-locked loop (FLL) for multiplying IMO frequency

- Integer and fractional peripheral clock dividers

? Quad SPI (QSPI)/Serial Memory Interface (SMIF)

- Execute-In-Place (XIP) from external quad SPI Flash

- On-the-fly encryption and decryption

- 4-KB cache for greater XIP performance with lower power

- Supports single, dual, quad, dual-quad, and octal interfaces with throughput up to 640 Mbps

? Segment LCD Drive

- Supports up to 83 segments and up to 8 commons

? Serial communication

- Nine run-time configurable serial communication blocks (SCBs)

? Eight SCBs: configurable as SPI, I2C, or UART

? One Deep Sleep SCB: configurable as SPI or I2C

- USB full-speed device interface

? Audio subsystem

- Two pulse density modulation (PDM) channels and one I2S channel with time division multiplexed (TDM) mode

? Timing and pulse-width modulation

- Thirty-two timer/counter/pulse-width modulators (TCPWM)

- Center-aligned, edge, and pseudo-random modes

- Comparator-based triggering of Kill signals

? Programmable analog

- 12-bit 1-Msps SAR ADC with differential and single-ended modes and 16-channel sequencer with result averaging

- Two low-power comparators available in Deep Sleep and Hibernate modes

- Built-in temperature sensor connected to ADC

- One 12-bit voltage-mode digital-to-analog converter (DAC) with < 2-μs settling time

- Two opamps with low-power operation modes

? Up to 84 programmable GPIOs

- Two Smart I/O? ports (16 I/Os) enable Boolean operations on GPIO pins; available during system Deep Sleep

- Programmable drive modes, strengths, and slew rates

- Six overvoltage-tolerant (OVT) pins

? Capacitive sensing

- CAPSENSE? provides best-in-class signal-to-noise ratio (SNR), liquid tolerance, and proximity sensing

- Enables dynamic usage of both self and mutual sensing

- Automatic hardware tuning (SmartSense)

? security Built into Platform Architecture

- ROM-based root of trust via uninterruptible “Secure Boot”

- Step-wise authentication of execution images

- Secured execution of code in execute-only mode for protected routines

- All Debug and Test ingress paths can be disabled

- Up to eight Protection Contexts

? Cryptography accelerator

- Hardware acceleration for symmetric and asymmetric cryptographic methods and hash functions

- True random number generation (TRNG) function

? Programmable digital

- Twelve programmable logic blocks, each with 8 Macrocells and an 8-bit data path (called universal digital

blocks or UDBs)

- Usable as drag-and-drop Boolean primitives (gates, registers), or as Verilog-programmable blocks

- Infineon-provided peripheral component library using UDBs to implement functions such as communication

peripherals (for example, LIN, UART, SPI, I2C, S/PDIF and other protocols), Waveform Generators, Pseudo-Random

Sequence (PRS) generation, and many other functions.

? Profiler

- Eight counters provide event or duration monitoring of on-chip resources

? Packages

- 124-BGA and 104-M-CSP; with USB

- 116-BGA, 104-M-CSP, and 68-QFN; no USB

? Device Identification and Revisions

- Product line ID (12-bit): 0x100

- Major/Minor Die Revision ID: 2/4

- Firmware Revisions: Rom Boot: 4.1, Flash Boot: 1.20.1.45 (see Boot Code section)

- This product line has a JTAG ID which is available through the SWJ interface. It is a 32-bit ID, where:

- The most significant digit is the device revision, based on the Major Die Revision

- The next four digits correspond to the part number, for example E4B0 as a hexadecimal number

- The three least significant digits are the manufacturer ID, in this case 069 as a hexadecimal number

- The Silicon ID system call can be used by firmware to get Silicon ID and ROM Boot data. For more information,

see the technical reference manual (TRM).

- The Flash Boot version can be read directly from a designated address 0x1600 2004. For more information,

see the technical reference manual (TRM).