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ARCHITECTURAL OVERVIEW

The high performance of the PIC12C5XX family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC12C5XX uses a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched on the same bus. Separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 12-bits wide making it possible to have all single word instructions. A 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions (33) execute in a single cycle (1?s @ 4MHz) except for program branches.

High-Performance RISC CPU:

? Only 33 single word instructions to learn

? All instructions are single cycle (1 ?s) except for program branches which are two-cycle

? Operating speed:

DC - 4 MHz clock input

DC - 1 ?s instruction cycle

? 12-bit wide instructions

? 8-bit wide data path

? Seven special function hardware registers

? Two-level deep hardware stack

? Direct, indirect and relative addressing modes for data and instructions

? Internal 4 MHz RC oscillator with programmable calibration

? In-circuit serial programming

Peripheral Features:

? 8-bit real time clock/counter (TMR0) with 8-bit programmable prescaler

? Power-On Reset (POR)

? Device Reset Timer (DRT)

? Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation

? Programmable code-protection

? 1,000,000 erase/write cycle EEPROM data memory

? EEPROM data retention > 40 years

? Power saving SLEEP mode

? Wake-up from SLEEP on pin change

? Internal weak pull-ups on I/O pins

? Internal pull-up on MCLR pin

? Selectable oscillator options:

- INTRC: Internal 4 MHz RC oscillator

- EXTRC: External low-cost RC oscillator

- XT: Standard crystal/resonator

- LP: Power saving, low frequency crystal

CMOS Technology:

? Low power, high speed CMOS EPROM/ROM technology

? Fully static design

? Wide operating voltage range

? Wide temperature range:

- Commercial: 0¡ãC to +70¡ãC

- Industrial: -40¡ãC to +85¡ãC

- Extended: -40¡ãC to +125¡ãC

? Low power consumption

- < 2 mA @ 5V, 4 MHz

- 15 ?A typical @ 3V, 32 KHz

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