利博·(集团)有限公司官网

Features

- Arm Cortex-A53 MPCore platform

Quad symmetric Cortex-A53 processors

? 32 KB L1 Instruction Cache

? 32 KB L1 Data Cache

? Media Processing Engine (MPE) with NEON technology supporting the Advanced

Single Instruction Multiple Data architecture:

? Floating Point Unit (FPU) with support of the VFPv4-D16 architecture

Support of 64-bit Armv8-A architecture

512 KB unified L2 cache

-Arm Cortex-M4 core platform

Low power microcontroller available for customer application:

? low power standby mode

? IoT features including Weave

? Manage IR or Wireless Remote

Cortex M4 CPU:

? 16 KB L1 Instruction Cache

? 16 KB L1 Data Cache

? 256 KB tightly coupled memory (TCM)

-Connectivity

One PCI Express (PCIe)

? Single lane supporting PCIe Gen2

? Dual mode operation to function as root complex or endpoint

? Integrated PHY interface

? Support L1 low power sub-state

Two USB 2.0 OTG controllers with integrated PHY interfaces:

? Spread spectrum clock support

Three Ultra Secure Digital Host Controller (uSDHC) interfaces:

? MMC 5.1 compliance with HS400 DDR signaling to support up to 400 MB/sec

? SD/SDIO 3.0 compliance with 200 MHz SDR signaling to support up to 100

MB/sec

? Support for SDXC (extended capacity)

One Gigabit Ethernet controller with support for Energy Efficient Ethernet (EEE),

Ethernet AVB, and IEEE 1588

Four Universal Asynchronous Receiver/Transmitter (UART) modules

Four I2C modules

Three ECSPI modules

-On-chip memory

Boot ROM (256 KB)

On-chip RAM (256 KB + 32 KB)

-GPIO and pin multiplexing

General-purpose input/output (GPIO) modules with interrupt capability

Input/output multiplexing controller (IOMUXC) to provide centralized pad control

-Power management

Temperature sensor with programmable trip points

Flexible power domain partitioning with internal power switches to support efficient

power management

-External memory interface

32/16-bit DRAM interfaces:

? LPDDR4 (up to 1.5 GHz)

? DDR4-2400

? DDR3L-1600

8-bit NAND-Flash, including support for Raw MLC/SLC devices, BCH ECC up to

62-bit, and ONFi3.2 compliance (clock rates up to 100 MHz and data rates up to 200

MB/sec)

eMMC 5.1 Flash (2 interfaces, uSDHC1 and uSDHC3)

SPI NOR Flash (3 interfaces)

FlexSPI with support for XIP (for ME in low-power mode) and parallel read mode of

two identical FLASH devices

-Multimedia

Video Processing Unit:

? 1080p60 VP9 Profile 0, 2 (10-bit)

? 1080p60 HEVC/H.265 Decoder

? 1080p60 AVC/H.264 Baseline, Main, High decoder

? 1080p60 VP8

? 1080p60 AVC/H.264 Encoder

? 1080p60 VP8

? TrustZone support

Graphic Processing Unit:

? GCNanoUltra for 3D acceleration

? GC320 for 2D acceleration

LCDIF Display Controller:

? Support up to 2 layers of overlay

? Support up to 1080p60 display through MIPI DSI

MIPI Interface:

? 4-lane MIPI CSI interface

? 4-lane MIPI DSI interface

Audio:

? S/PDIF input and output, including a new Raw Capture input mode

? Five synchronous audio interface (SAI) modules supporting I2S, AC97, TDM,

codec/DSP, and DSD interfaces, including one SAI with 8 Tx and 8 Rx lanes, one

SAI with 4 Tx and 4 Rx lanes, two SAI with 2 Tx and 2 Rx lanes, and one SAI with

1 Tx and 1Rx lane. Support over 20 channels of audio subject to I/O limitations.

? 8-Channel Pulse Density Modulation (PDM) input

-System debug

Arm CoreSight debug and trace architecture

Trace Port Interface Unit (TPIU) to support off-chip real-time trace

Embedded Trace FIFO (ETF) with 4 KB internal storage to provide trace buffering

Unified trace capability for Quad Cortex-A53 and Cortex-M4 CPUs

Cross Triggering Interface (CTI)

Support for 5-pin (JTAG) debug interface

-Security

Resource Domain Controller (RDC) supports four domains and up to eight regions of

DDR

Arm TrustZone (TZ) architecture:

? Support Arm Cortex-A53 MPCore TrustZone

On-chip RAM (OCRAM) secure region protection using OCRAM controller

High Assurance Boot (HAB)

Cryptographic acceleration and assurance (CAAM) module and Assurance Module:

? Support Widevine and PlayReady content protection

? Public Key Cryptography (PKHA) with RSA and Elliptic Curve (ECC) algorithms

? Real-time integrity checker (RTIC)

? DRM support for RSA, AES, 3DES, DES

? Side channel attack resistance

? True random number generation (RNG)

? Manufacturing protection support

Secure non-volatile storage (SNVS):

? Secure real-time clock (RTC)

Secure JTAG controller (SJC)