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DESCRIPTION

The 74ALVT162823 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity.

FEATURES

? Two sets of high speed parallel registers with positive

edge-triggered D-type flip-flops

? 5V I/O Compatible

? Ideal where high speed, light loading, or increased fan-in are

required with MOS microprocessors

? Live insertion/extraction permitted

? Power-up 3-State

? Power-up Reset

? Output capability: +12mA/–12mA

? Latch-up protection exceeds 500mA per Jedec Std 17

? ESD protection exceeds 2000 V per MIL STD 883 Method 3015

and 200 V per Machine Model

? Bus hold data inputs eliminate the need for external pull-up

resistors to hold unused inputs

? Outputs include series resistance of 30? making external

termination resistors unnecessary