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? Dual 10-bit resolution

? 650 Msps maximum update rate

? Selectable 2?, 4? or 8? interpolation

filters

? Input data rate up to 312.5 Msps

? Very low noise cap free integrated PLL

? 32-bit programmable NCO frequency

? Four JESD204A serial input lanes

? 1.8 V and 3.3 V power supplies

? LVDS compatible clock inputs

? IMD3: 80 dBc; fs = 640 Msps;

fo = 140 MHz

? ACPR: 64 dBc; two carriers WCDMA;

fs = 640 Msps; fo = 133 MHz

? Typical 1.20 W power dissipation at

4? interpolation, PLL off and 640 Msps

? Power-down mode and Sleep modes

? Differential scalable output current from

1.6 mA to 22 mA

? On-chip 1.29 V reference

? External analog offset control

(10-bit auxiliary DACs)

? Internal digital offset control

? Inverse (sin x) / x function