利博·(集团)有限公司官网

FEATURES

? RSDSTM (Reduced Swing Differential Signaling) interface

? 480 Outputs

? Input of 8 bits (gradation data) by 3 dots with double clock edge

? Capable of outputting 256 values by means of 9-by-2 external power modules (18 units) and a D/A converter

? Logic power supply voltage (VDD1) : 2.7 to 3.6 V

? Driver power supply voltage (VDD2) : 10.5 to 13.5 V

? High-speed data transfer : fCLK = 85 MHz MAX. (Internal data transfer speed when operating at VDD1 = 2.7 V)

? Output dynamic range : VSS2 + 0.1 V to VDD2 – 0.1 V

? Apply for dot-line inversion, n-line inversion and column line inversion

? Output voltage polarity inversion function (POL)

? Input data inversion function (INV)

? ControIlable charge sharing function (MODE)