利博·(集团)有限公司官网

FEATURES

? CMOS level input

? 384 outputs

? Input of 6 bits (gradation data) by 6 dots

? Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter

? Logic power supply (VDD1): 3.3 V ± 0.3 V

? Driver power supply (VDD2): 11.0 V V

? High-speed data transfer: fCLK = 55 MHz (internal data transfer speed when operating at 3.0 V)

? Output dynamic range VSS2 + 0.1 V to VDD2 – 0.1 V

? Apply for only dot-line inversion

? Single bank arrangement is possible (POL)

? Display data inversion function (POL2)

? Low power control function (LPC)

? Single-sided mounting (Slim TCP)