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Features

? Double-data-rate architecture; two data transfers per clock cycle

? Bidirectional data strobe(DQS)

? Four banks operation

? Differential clock inputs(CK and CK)

? DLL aligns DQ and DQS transition with CK transition

? MRS cycle with address key programs

-. Read latency 2, 2.5 (clock)

-. Burst length (2, 4, 8)

-. Burst type (sequential & interleave)

? All inputs except data & DM are sampled at the positive going edge of the system clock(CK)

? Data I/O transactions on both edges of data strobe

? Edge aligned data output, center aligned data input

? LDM,UDM/DM for write masking only

? Auto & Self refresh

? 15.6us refresh interval(4K/64ms refresh)

? Maximum burst refresh cycle : 8

? 66pin TSOP II package