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Features

? Provides jitter attenuation and frequency

translation between SONET/PDH and

Ethernet

? Supports ITU-T G.8262 Synchronous

Ethernet equipment slave clock (EEC

option 1 and 2) requirements with

optional Stratum 3 compliant timing card

clock source

? Two clock inputs/two clock outputs

? Input frequency range: 8 kHz¨C644 MHz

? Output frequency range: 8 kHz¨C644 MHz

? Ultra low jitter:

0.23 ps RMS (1.875¨C20 MHz)

0.47 ps RMS (12 kHz¨C20 MHz)

? Simple pin control interface

? Selectable loop bandwidth for jitter

attenuation: 60 to 8.4 kHz

? Automatic/Manual hitless switching

and holdover during loss of inputs

clock

? Programmable output clock signal

format: LVPECL, LVDS, CML or

CMOS

? 40 MHz crystal or XO reference

? Single supply: 1.8, 2.5, or 3.3 V

? On-chip voltage regulator with high

PSRR

? Loss of lock and loss of signal alarms

? Small size: 6 x 6 mm, 36-QFN

? Wide temperature range: ¨C40 to

+85 ?C